The present invention relates to a method and system for clock tree synthesis of integrated circuits.
With the advent of deep sub-micron technologies, the design closure for very large integrated circuits has become complicated. As a result, System-on-chip (SoC) designs are implemented with a hierarchical design flow. The hierarchical design flow allows multiple teams to work on different parts of the design concurrently and independently. Further, the hierarchical design flows are scalable to handle designs for integrated circuits containing up to 100 million gates.
One fundamental problem with a hierarchical design flow is the large number of iterations required for meeting skew specifications. A skew is referred to as the time difference between the arrival times of each clock signal pulse at any two sinks. As a result, an efficient method for clock tree synthesis of hierarchical design flows is required. Clock tree synthesis designs a group of clock trees to be incorporated into an integrated circuit design for conveying separate clock signals to clock sinks, within the integrated circuit, with a pre-determined maximum group skew. The clock trees are referred to as the branching network of a conductor and a buffer, to fan out a clock signal arriving at one of its input terminals, to each of the sinks that are clocked by that clock signal.
Several methods have been conventionally used for clock tree synthesis of hierarchical design flows. The major concerns of such methods are minimizing clock skew and optimizing clock buffers. This results in meeting skew specifications and minimizing clock tree power dissipation. Variations in the clock signal's arrival time at the clock inputs of various logic elements cause a clock skew. While designing a clock tree, the performance specifications that are timing-related and affect other chip design goals are crucial and need to be considered. Clock tree timing specifications include clock latency, skew, and jitter. Non-timing specifications include power dissipation, signal integrity, and reliability due to electro migration effects in the clock lines.
Several methods have been conventionally used by chip designers for clock tree synthesis of hierarchical design flows. One such method is the bottom-up methodology. This method firstly designs the block-level of the clock tree, i.e., the designing is done individually for each block. Subsequently, the full chip is designed based on the block-level results. A block-level clock tree tends to be over-designed, and the runtime can become very long. Further, the bottom-up method provides lesser uniform path distance between the buffers at the top-level of the clock tree. As a result, balancing the clock tree becomes difficult. Balancing the clock tree refers to the positioning of each fan-out buffer, so as to minimize the variation in the signal path distances from each fan-out buffer, to the next lower level fan-out buffer or sink it drives.
This problem of lesser uniform path distance at the top-level of the clock tree is addressed by another conventionally used method, referred to as top-down methodology. This method firstly designs the top-level of the clock tree and then the block-levels are designed based on the top-level design. Subsequently, the full chip is balanced based on the top-level result. The top-down methodology provides a relatively uniform path distance between the buffers at the top-level of the clock tree. However, at the block-levels of the clock tree the path distance becomes less uniform. As a result, it becomes more difficult to balance the clock tree, and the convergence is achieved slowly. Further, the top-down methodology is unable to obtain an accurate clock budgeting for both top-level and block-level. This leads to several iterations to refine the result, and the quality and runtime of the integrated circuits is degraded. Furthermore, the complexity of the hierarchical design flow increases tremendously.
In light of the foregoing discussion, a need exists for reducing the number of iterations required for clock tuning, between a top-level clock tree and a block-level clock tree, in a hierarchical design clock tree synthesis. The present invention addresses such a need.